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<srw:recordPosition>5</srw:recordPosition><srw:recordData><mods xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://www.loc.gov/mods/v3" version="3.6" xsi:schemaLocation="http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-6.xsd"><titleInfo><title>1029.1-1998 IEEE Standard for Vhdl Waveform and Vector Exchange to Support Design and Test Verification (Waves) Language Reference Manual</title></titleInfo><name type="corporate"><namePart>Institute of Electrical and Electronics Engineers,</namePart><role><roleTerm type="text">author,</roleTerm></role><role><roleTerm type="text">issuing body.</roleTerm></role></name><typeOfResource>text</typeOfResource><genre>text</genre><genre authority="marcgt">book</genre><originInfo><place><placeTerm type="code" authority="marccountry">xx</placeTerm></place><place><placeTerm type="text">[Place of publication not identified]</placeTerm></place><publisher>IEEE</publisher><dateIssued keyDate="yes">1998</dateIssued><issuance>monographic</issuance></originInfo><language><languageTerm authority="iso639-2b" type="code">eng</languageTerm></language><physicalDescription><form authority="marccategory">electronic resource</form><form authority="marcsmd">remote</form><extent>1 online resource (viii, 191 pages)</extent><form type="media">computer</form><form type="carrier">online resource</form></physicalDescription><abstract>A report is given on the IEEE Standard for VHDL waveform and vector exchange to support design and test verification (WAVES) Language Reference Manual. This standard is a formal notation intended for use in all phases of the development of electronic systems. Because it is both machine-readable and human-readable, it supports the verification and testing of hardware designs; the communication of hardware design and test verification data; and the maintenance, modification, and procurement of hardware systems. This standard provides the syntactic and semantic framework for the unambiguous expression and aggregation of digital test data and timing information necessary to completely describe a test or set of tests for a digital system. WAVES digital test data (stimulus and expected responses) is described at the logic level. Voltage and current values are not described by WAVES and are beyond the scope of this standard.</abstract><tableOfContents>Keywords -- Metrics -- Versions.</tableOfContents><note>Bibliographic Level Mode of Issuance: Monograph</note><note type="language">English</note><subject authority="lcsh"><topic>Electronic systems</topic><topic>Testing.</topic></subject><subject authority="lcsh"><topic>Semiconductors</topic><topic>Design and construction.</topic></subject><subject authority="lcsh"><topic>VHDL (Computer hardware description language)</topic></subject><classification authority="lcc">TK7870.23 .I578 1998</classification><classification authority="ddc" edition="23">621.381</classification><relatedItem type="otherFormat"><identifier type="isbn">0-7381-1445-6</identifier></relatedItem><identifier type="isbn">0-7381-3945-9</identifier><identifier type="isbn">0-7381-1446-4</identifier><extension><vl:originInfo xmlns:vl="http://visuallibrary.net/vl" displayLabel="dc"><dateCreated encoding="w3cdtf" point="start">1998</dateCreated></vl:originInfo><vlz:info xmlns:vlz="http://visuallibrary.net/vlz/1.0/" version="0"/></extension><recordInfo><recordContentSource authority="marcorg">PQKB</recordContentSource><recordCreationDate encoding="marc">160829</recordCreationDate><recordChangeDate encoding="iso8601">20210807000313.0</recordChangeDate><recordIdentifier source="erara_alma_phz">99116731750005521</recordIdentifier><recordOrigin>Converted from MARCXML to MODS version 3.6 using MARC21slim2MODS3-6.xsl
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<srw:recordPosition>9</srw:recordPosition><srw:recordData><mods xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://www.loc.gov/mods/v3" version="3.6" xsi:schemaLocation="http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-6.xsd"><titleInfo><title>1149.7-2022 - IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture /</title></titleInfo><name type="corporate"><namePart>Institute of Electrical and Electronics Engineers,</namePart><role><roleTerm type="text">author,</roleTerm></role><role><roleTerm type="text">issuing body.</roleTerm></role></name><typeOfResource>text</typeOfResource><genre authority="rdacontent">text</genre><genre authority="marcgt">book</genre><originInfo><place><placeTerm type="code" authority="marccountry">nyu</placeTerm></place><place><placeTerm type="text">New York :</placeTerm></place><publisher>IEEE,</publisher><dateIssued>2022.</dateIssued><dateIssued encoding="w3cdtf" keyDate="yes">2022</dateIssued><issuance>single unit</issuance></originInfo><language><languageTerm authority="iso639-2b" type="code">eng</languageTerm></language><physicalDescription><form authority="marccategory">electronic resource</form><form authority="marcsmd">remote</form><extent>1 online resource (1048 pages)</extent><form type="media" authority="rdamedia">computer</form><form type="carrier" authority="rdacarrier">online resource</form></physicalDescription><abstract>Circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 is described in this standard. The circuitry uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of IEEE 1149.7 Test Access Ports (TAP.7s), T0 to T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes IEEE 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.</abstract><note type="statement of responsibility" altRepGroup="00">IEEE.</note><subject authority="lcsh"><topic>Electronic controllers.</topic></subject><subject authority="lcsh"><topic>Debugging in computer science.</topic></subject><subject authority="lcsh"><topic>Boundary scan testing.</topic></subject><classification authority="lcc">TK7881.2 .I578 2022</classification><classification authority="ddc" edition="23">621.46</classification><identifier type="isbn">1-5044-8875-X</identifier><identifier type="doi">10.1109/IEEESTD.2022.9919140</identifier><extension><vl:originInfo xmlns:vl="http://visuallibrary.net/vl" displayLabel="dc"><dateCreated encoding="w3cdtf" point="start">2022</dateCreated></vl:originInfo><vlz:info xmlns:vlz="http://visuallibrary.net/vlz/1.0/" version="0"/></extension><recordInfo><descriptionStandard>rda</descriptionStandard><recordContentSource authority="marcorg">NjHacI</recordContentSource><recordCreationDate encoding="marc">231214</recordCreationDate><recordChangeDate encoding="iso8601">20231214123445.0</recordChangeDate><recordIdentifier source="erara_alma_phz">99116818859505521</recordIdentifier><recordOrigin>Converted from MARCXML to MODS version 3.6 using MARC21slim2MODS3-6.xsl
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<srw:recordPosition>10</srw:recordPosition><srw:recordData><mods xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://www.loc.gov/mods/v3" version="3.6" xsi:schemaLocation="http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-6.xsd"><titleInfo><title>115-2019 - IEEE Guide for Test Procedures for Synchronous Machines Including Acceptance and Performance Testing and Parameter Determination for Dynamic Analysis - Redline /</title></titleInfo><name type="corporate"><namePart>Institute of Electrical and Electronics Engineers,</namePart><role><roleTerm type="text">author,</roleTerm></role><role><roleTerm type="text">issuing body.</roleTerm></role></name><typeOfResource>text</typeOfResource><genre authority="rdacontent">text</genre><genre authority="marcgt">book</genre><originInfo><place><placeTerm type="code" authority="marccountry">nyu</placeTerm></place><publisher>IEEE</publisher><dateIssued>2020-05-13</dateIssued><place><placeTerm type="text">New York :</placeTerm></place><publisher>IEEE,</publisher><dateIssued>2020.</dateIssued><dateIssued encoding="w3cdtf" keyDate="yes">2020</dateIssued><issuance>single unit</issuance></originInfo><language><languageTerm authority="iso639-2b" type="code">eng</languageTerm></language><physicalDescription><form authority="marccategory">electronic resource</form><form authority="marcsmd">remote</form><extent>1 online resource (497 pages)</extent><form type="media" authority="rdamedia">computer</form><form type="carrier" authority="rdacarrier">online resource</form></physicalDescription><abstract>Instructions for conducting generally applicable and accepted tests to determine the performance characteristics of synchronous machines are contained in this guide. Although the tests described are applicable in general to synchronous generators, synchronous motors (larger than fractional horsepower), synchronous condensers, and synchronous frequency changers, the descriptions make reference primarily to synchronous generators and synchronous motors.</abstract><note type="statement of responsibility" altRepGroup="00">IEEE.</note><subject authority="lcsh"><topic>Synchronous generators.</topic></subject><subject authority="lcsh"><topic>Electric machinery</topic><topic>Testing.</topic></subject><classification authority="lcc">TK2765 .I578 2020</classification><classification authority="ddc" edition="23">621.3134</classification><identifier type="isbn">1-5044-6695-0</identifier><identifier type="isbn">9781504466950</identifier><identifier type="isbn">1504466950</identifier><extension><vl:originInfo xmlns:vl="http://visuallibrary.net/vl" displayLabel="dc"><dateCreated encoding="w3cdtf" point="start">2020</dateCreated></vl:originInfo><vlz:info xmlns:vlz="http://visuallibrary.net/vlz/1.0/" version="0"/></extension><recordInfo><descriptionStandard>rda</descriptionStandard><recordContentSource authority="marcorg">NjHacI</recordContentSource><recordCreationDate encoding="marc">231214</recordCreationDate><recordChangeDate encoding="iso8601">20260624213116.0</recordChangeDate><recordIdentifier source="erara_alma_phz">99116732015305521</recordIdentifier><recordOrigin>Converted from MARCXML to MODS version 3.6 using MARC21slim2MODS3-6.xsl
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